IB Computer Science A1.1: Computer hardware and operation

New IB Computer Science syllabus · first exams May 2027 · Theme A · SL & HL (A1.1.3 and A1.1.6 HL only)

A1.1 is the first sub-unit of A1 Computer fundamentals (11 hours SL, 18 hours HL). It covers CPU components, primary and secondary memory, the fetch–decode–execute cycle, pipelining, compression and cloud computing.

Key points

A1.1.1 CPU components, registers and buses

• Control unit (CU): directs the processor. It fetches and decodes instructions and controls the sequence of operations, but does not process data itself.
• Arithmetic logic unit (ALU): performs arithmetic (addition, subtraction, multiplication) and logic operations (AND, OR, NOT, comparisons).
• The five key registers:
  • PC (program counter): address of the next instruction; incremented after each fetch.
  • IR (instruction register): the instruction currently being decoded and executed.
  • MAR (memory address register): the address being read from or written to; connected to the address bus.
  • MDR (memory data register): the data moving to or from memory; a buffer between CPU and RAM, connected to the data bus.
  • AC (accumulator): stores the results of ALU operations.
• The three buses:
  • Address bus: one way, CPU → memory. Its width sets how much memory can be addressed (a 32-bit bus gives 2³² = 4 GB).
  • Data bus: both ways; carries the data. Its width sets how much moves per transfer.
  • Control bus: carries control signals such as read/write, clock and interrupts.
• Processors: single-core (one instruction stream at a time), multi-core (several independent cores, each with its own CU and ALU, running in parallel), co-processors (specialised processors that take work off the main CPU).

A1.1.2 The role of a GPU

A GPU has thousands of smaller, simpler cores that apply the same operation to many data items at once (SIMD), with high memory bandwidth. It is optimised for throughput rather than latency, which suits video game rendering, training AI models, large simulations such as weather forecasting, and video processing.

A1.1.3 CPU vs GPU (HL only)

• Design philosophy: a CPU is optimised for low latency, finishing individual tasks quickly in sequence. A GPU is optimised for high throughput, finishing as many tasks as possible in parallel.
• Cores: a CPU has a few powerful, complex cores; a GPU has thousands of simpler ones.
• Memory: a CPU relies on a large, fast cache hierarchy to minimise latency; a GPU relies on high-bandwidth memory.
• Working together: the CPU divides the task, sends data and instructions to the GPU, and the GPU returns the results of its parallel processing.

A1.1.4 Primary memory

• RAM: volatile, read/write; holds the programs and data currently in use.
• ROM: non-volatile, read-only; stores the firmware (BIOS/UEFI) needed to start the computer.
• Cache: very fast memory in or near the CPU, storing frequently used data and instructions so the CPU doesn't go to RAM every time.
  • L1: smallest and fastest, inside each core.
  • L2: larger, per core.
  • L3: largest and slowest of the three, shared by all cores, and the last level before RAM.
• Cache hit: the data is found in cache, so access is immediate.
• Cache miss: the data must be fetched from slower RAM, then loaded into cache for next time.

A1.1.5 The fetch, decode and execute cycle

1. Fetch: the PC's address is copied to the MAR. The instruction at that address is placed in the MDR, then moved to the IR. The PC is incremented.
2. Decode: the CU reads the instruction in the IR, works out the operation and operands, and sends control signals.
3. Execute: the ALU carries out the operation. The result goes to the accumulator, and may be written back to memory.

Buses during fetch: the address bus carries the address from the MAR to memory, the control bus signals a read, and the data bus carries the instruction back to the MDR. The cycle is synchronised by the clock: a 3 GHz CPU completes 3 billion cycles per second.

A1.1.6 Pipelining (HL only)

Pipelining works like an assembly line. While instruction 1 executes, instruction 2 is decoded and instruction 3 is fetched. The stages are fetch, decode, execute, write-back. Once the pipeline is full, roughly one instruction finishes every clock cycle. In a multi-core processor, each core runs its own pipeline, so different instruction streams run in true parallel. Branch instructions can stall the pipeline, which is why CPUs use branch prediction.

A1.1.7 Secondary storage

Secondary storage is non-volatile, larger and slower than primary memory.

Internal:

• SSD: flash memory with no moving parts; fast, so it's used as the main OS drive.
• HDD: magnetic platters; cheaper per GB, used for backups and media.
• eMMC: flash memory soldered to the board; found in budget laptops, Chromebooks and phones.

External:

• External SSD or HDD: portable backup and moving large files.
• Optical drives: archiving and software distribution.
• Flash drives: quick file transfer.
• Memory cards: cameras, phones and drones.
• NAS: shared storage over a network.

A1.1.8 Compression

• Lossless: the original is perfectly reconstructed. Used for text, executables, medical images and legal documents.
  • Run-length encoding (RLE): stores repeated values as a count and the value. WWWWWWBBBWWWW becomes 6W3B4W, which is 6 characters instead of 13.
• Lossy: some data is permanently discarded, giving much smaller files. Used for photos, music and video.
  • Transform coding: converts data into another representation (for example the frequency domain, as in JPEG and MP3) and discards the fine detail people can't perceive.

A1.1.9 Cloud computing: SaaS, PaaS, IaaS

• SaaS: the provider manages everything and you just use the application (for example Google Docs or Microsoft 365). Least control.
• PaaS: the provider manages the infrastructure and OS, and you build and deploy your own applications (for example Google App Engine).
• IaaS: the provider supplies virtual hardware, and you control the OS, applications and data (for example AWS EC2). Most control and flexibility, but more expertise needed.

Exam-style question

Describe the role of the program counter (PC) and the memory address register (MAR) in the fetch stage of the fetch–decode–execute cycle. [4]

Mark scheme

Award [1] for each point, up to [4]:

• The PC holds the address of the next instruction to be fetched;
• Its value is copied to the MAR;
• The MAR sends the address via the address bus to main memory;
• The PC is then incremented to point to the next instruction;

Award marks for any equivalent correct point, even if worded differently.

Common mistakes that cost marks

• Mixing up the MAR and MDR. The MAR holds an address; the MDR holds data.
• Forgetting that the PC is incremented. It is often the missing final mark.
• Saying the address bus is two-way. It only goes from the CPU to memory. The data bus is the two-way one.
• Answering an "Explain" question (A1.1.4) with a list. Give the purpose and the reason for each memory type.
• Choosing lossy compression where exact data matters, such as medical X-rays or text files.

Frequently asked questions

Is A1.1 studied at SL or HL?
Both. A1.1.3 (CPU vs GPU) and A1.1.6 (pipelining) are HL only.

Which paper assesses A1.1?
A1.1 is part of Theme A, which is assessed in Paper 1.

How much time is spent on A1 Computer fundamentals?
The IB guide recommends 11 hours at SL and 18 hours at HL for the whole of A1.

Go further

• Practise A1.1 with instant marking on ExamHaus. Write your answer and get it marked in seconds against the mark scheme. → examhaus.com
• Full A1.1 presentation and 28-question bank with mark scheme on CS Exam Ready. → csexamready.com/resources/ib-diploma
• IB CS mock exams: Paper 1 & 2, SL & HL. → examhaus.com/mock-exams